Memory devices are conventionally provided in computers and other electronic devices in the form of semiconductor-based integrated circuits. There are many different types of memory devices including random-access memory (RAM), read-only memory (ROM), synchronous dynamic random-access memory (SDRAM), dynamic random-access memory (DRAM), and non-volatile memory. As the performance and complexity of electronic systems increase, the requirement for additional memory in memory systems also increases. The trend in the semiconductor industry is toward smaller memory devices that may be fabricated as high-density circuits on a single semiconductor chip. Miniaturization of transistor devices and circuits may be achieved by reducing the size of at least some of the features of devices so that the resulting devices occupy a smaller surface area of a wafer.
To reduce costs of fabricating such high-density memory arrays, the parts count must be kept to a minimum. This means being able to achieve a higher density of memory on a single chip instead of by stacking separate memory chips. However, as memory devices decrease in size while increasing the number of memory cells in a memory array, the number of internal connections necessary to operate each memory device also increases.
For example, in non-volatile memory (e.g., NAND flash memory), one way to increase memory density is by using a vertical memory array, which is also referred to as a three-dimensional (3-D) array. Such vertical memory arrays are disclosed in, for example, U.S. Patent Application Publication No. 2007/0252201 to Kito et al., now U.S. Pat. No. 7,936,004, issued May 3, 2011. Conventional vertical memory arrays require electrical connection between the conductive plates and access lines (e.g., word lines) so that memory cells in the array may be uniquely selected for writing or reading functions by control units. One type of vertical memory array includes semiconductor pillars that extend through holes in layered conductive plates (also referred to as word line plates or control gate plates), with dielectric materials at each junction of the pillars and the conductive plates. Thus, multiple transistors can be formed along each pillar. This structure enables a greater number of transistors to be located in a unit of die area by building the array upwards (vertically) on a die. However, in such a device each memory cell must include multiple conductive connections (e.g., word lines, bit lines, select gates, etc.) in order to read, write, and erase each individual memory cell or plurality of memory cells. In such a memory array having a high density of memory cells, it may be difficult to provide the connections to each memory cell in an effective and efficient manner.
As the number of tiers in the memory cell, and thus the number of conductive plates, increases so does the number of conductive connections required to connect the conductive plates. The conductive connections may increase until there is not enough room in a block dimension (e.g., span) to accommodate all of the pass conductive connections, at which point the size (e.g., pitch) of the stacked memory array needs to be increased to accommodate the extra conductive connections and control units. For example, in a 3-D NAND array, block pitch is dictated by the need to route the word line signals through conductive connections. Increasing the number of memory cells in the array generally requires that the block pitch also be increased to accommodate the additional plates and associated connections. Such an increase in the number of plates also increases the total word line (WL) capacitance requiring that the pump work harder, thereby, using higher power and reducing performance. Further, the increase in the number of drain selectors also proportionally increases, which increase may be problematic for devices requiring a lower amount of pages per block (e.g., devices where a finer erase granularity is required).